fn3110 rev 2.00 page 1 of 8 march 2001 fn3110 rev 2.00 march 2001 hi-dac80v 12-bit, low cost, monolithic d/a converter datasheet the hl-dac80v is a monolithic direct r eplacement for the popular dac80 and ad dac80. single chip construction along with several design innovations make the hl-dac80v the optimum choice for low cost, high reliability applications. intersil unique dielectric isol ation (dl) processing reduces internal parasitics resultin g in fast switching times and minimum glitch. on board span resistors are provided for good tracking over temperatur e, and are laser trimmed to high accuracy. internally the hl-dac80v eliminates code dependent ground currents by routing current fro m the positive supply to the internal ground node, as dete rmined by an auxiliary r2r ladder. this results in a cancellation of code dependent ground currents allowing virtually zero variation in current through the package common, pin 21. the hl-dac80v is available as a voltage output device which is guaranteed over the 0 o c to 75 o c temperature range. it includes a buried zener referenc e featuring a low temperature coefficient as well as an on board operational amplifier. the hl-dac80v requires only two power supplies and will operate in the range of ? (11.4v to 16.5v). features ? dac 80v alternative source ? monolithic construction ? fast settling time (typ) . . . . . . . . . . . . . . . . . . . . . . 1.5 ? s ? guaranteed monotonicity ? wafer laser trimmed linearity, gain, offset ? span resistors on-chip ? on-board reference ? supply operation . . . . . . . . . . . . . . . . . . . . . . . . . . . ? 12v applications ? high speed a/d converters ? precision instrumentation ? crt display generation pinout hi-dac80v (pdip) top view ordering information part number temp. range ( o c) package pkg. no. HI3-DAC80V-5 0 to 75 24 ld pdip e24.6 1 2 3 4 5 6 7 8 9 10 11 12 (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 (lsb) bit 12 16 17 18 19 20 21 22 23 24 15 14 13 6.3v ref out +v s common a junction 20v range bipolar offset v out -v s nc gain adjust 10v range ref input
hi-dac80v fn3110 rev 2.00 page 2 of 8 march 2001 functional block diagram 8k 1k 1k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 1k 2k 8k 8k 8k ground current cancel- lation circuit + - v out 5k span ? junction control amp 12.6k 8k gain adjust 6.3k 12.6k bipolar offset ref out common in + - +v s bit 1 in (msb) digital input level shi fters and switch drivers bit 12 in (lsb) 5k 20v span r 10v span r -v s + -
hi-dac80v fn3110 rev 2.00 page 3 of 8 march 2001 absolute maximum ratings thermal information power supply inputs +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+20v -v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20v reference input (pin 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v s output drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5ma digital inputs (bits 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . -1v to +v s operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 1) ? ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 maximum power dissipation pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c die characteristics process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mounted on a low effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details. electrical specifications t a = 25 o c, v s ? 12v to ? 15v (note 5), pin 16 shorted to pin 24, unless otherwise specif ied parameter test conditions min typ max units system performance resolution - - 12 bits accuracy (note 3) linear error full temperature - ? 1 / 4 ? 1 / 2 lsb differential linearity error full temperature - ? 1 / 2 ? 3 / 4 lsb monotonicity full temperature guaranteed gain error full temperature (notes 2, 4) - ? 0.1 ? 0.3 % fsr offset error full temperature (note 2) ? 0.05 ? 0.15 % fsr analog output output ranges (see figure 2 and table 2) - ? 2.5 - v - ? 5- v - ? 10 - v -0 to 5- v - 0 to 10 - v output current ? 5- -ma output resistance - 0.05 - ? short circuit duration to common continuous - drift (note 3) total bipolar dri ft (includes gain, offset and linearity drifts) full temperature - - ? 20 ppm/ o c total error unipolar full temperature (note 6) - ? 0.08 ? 0.15 % fsr bipolar full temperature (note 6) - ? 0.06 ? 0.1 % fsr gain with internal reference - ? 15 ? 30 ppm/ o c without internal reference - ? 7 - ppm/ o c
hi-dac80v fn3110 rev 2.00 page 4 of 8 march 2001 unipolar offset - ? 1 ? 3 ppm/ o c bipolar offset - ? 5 ? 10 ppm/ o c conversion speed settling time full scale transition all bits on to off or off to on to ? 0.01% or fsr (note 3) with 10k feedback - 3 - ? s with 5k feedback - 1.5 - ? s for 1 lsb change - 1.5 - ? s slew rate 10 15 - v/ ? s internal reference output voltage 6.250 +6.3 6.350 v output impedance - 1.5 - ? external current - - +2.5 ma tempco of drift - 5 - ppm/ o c digital input (note 2) logic levels logic 1 ttl compatible at +1 ? a+2-+5.5v logic 0 ttl compatible at -100 ? a0 -+0.8v power supply sensitivity (notes 3, 5) +15v supply - 0.001 0.002 % fsr / %v s -15v supply - 0.001 0.002 % fsr / %v s power supply characteristics (note 5) voltage range +v s full temperature +11.4 +15 +16.5 v -v s full temperature -11.4 -15 -16.5 v current +i s full temperature, v s = ? 15v - +12 +15 ma -i s full temperature, v s = ? 15v - -15 -20 ma notes: 2. adjustable to zero using external potentiometers. 3. see definitions. 4. fsr is full scale range: and is 20v for ? 10v range, 10v for ? 5v range, etc. 5. the hi-dac80v will operate with supply voltages as low as ? 11.4v. it is recommended that output voltage range -10v to +10v not be used if the supply voltages are less than ? 12.5v. 6. with gain and offset errors adjusted to zero at 25 o c. electrical specifications t a = 25 o c, v s ? 12v to ? 15v (note 5), pin 16 shorted to pin 24, unless otherwise specif ied (continued) parameter test conditions min typ max units
hi-dac80v fn3110 rev 2.00 page 5 of 8 march 2001 definitions of specifications digital inputs the hl-dac80v accepts digital in put codes in complementary binary, complementary offset binary, and complementary twos complement binary. settling time that interval between application of a digital step input, and final entry of the analog output within a specified window abou t the settled value. intersil co rporation usually specifies a unipolar 10v full scale step, to be measured from 50% of the input digital transition, and a window of ? 1 / 2 lsb about the final value. the device output is then rated according to the worst (longest settling) case: low to hi gh, or high to low. in a 12-b it system ? 1 / 2 lsb = ? 0.012% of fsr. thermal drift thermal drift is based on measurements at 25 o c, at high (t h ) and low (t l ) temperatures. drift calc ulations are made for the high (t h -25 o c) and low (25 o c-t l ) ranges, and the larger of the two values is given as a spe cification representing worst case drift. gain drift, offset drift, referen ce drift and total bipolar dri ft are calculated in par ts per million per o c as follows: note: fsr = full scale output voltage - zero scale output voltag e. ? fsr = fsr (t h ) - fsr (25 o c), or fsr (25 o c) - fsr (t l ). v o = steady state response to any input code. total bipolar drift (tbd) is the variation of output voltage wi th temperature, in the bipolar mode o f operation. it represents th e net effect of drift in gain, offset, linearity and reference voltage. total bipolar drift val ues are calculated, based on measurements as explained above. gain and offset need not be calibrated to zero at 25 o c. the specified limits for tbd apply for any input code and for any power supply setting within the specified operating range. accuracy linearity error (short for integral li nearity error. also, sometimes called integral nonl inearity and nonlinearity.) the maximum deviation of the ac tual transfer characteristic from an ideal straight line . the ideal line is positioned according to end-point linearity for d/a converter products fro m intersil corporation, i.e., the line is drawn between the end- points of the actual transfer characteristic (codes 00...0 and 11...1). differential linearity error the difference between one lsb and the output voltage change corresponding to any two consecutive codes. a differential nonlinearity of ? 1 lsb or less guarantees monotonicity. monotonicity the property of a d/a c onverters transfer function which guarantees that the output derivative will not change sign in response to a sequence of increasing (or decreasing) input codes. that i s, the only output response to a code change is to remain constant, increase for increasing code, or decrease fo r decreasing code. total error the net output error resu lting from all internal effects (primarily non-ideal gain, offset, linearity and reference voltage). supply voltages may be set to any values within the specified operating range. gain and offset errors must be calibrated to zero at 25 o c. then the specified limits for total error apply for any inpu t code and for any temperature within the specified operating range. power supply sensitivity power supply sensitivity is a measure of the change in gain and offset of the d/a converter resulting from a change in -v s , or +v s supplies. it is specifi ed under dc conditions and expressed as ful l scale range percent of change divided by power supply percent change. glitch a glitch on the output of a d/a converter is a transient spike resulting from unequal internal o n-off switching times. worst case glitches usually occur at half-scale, i.e., the major carr y code transition from 011...1 t o 100...0 or vic e versa. for example, if turn on is greater t han off for 011... 1 to 100...0, an intermediate state of 000...0 exists, such th at, the output momentarily glitches toward ze ro output. matched switching table 1. digital input analog output comple- mentary straight binary comple- mentary offset binary comple- mentary twos complement ? msb...lsb 000...000 + full scale + full scale -lsb 100...000 mid scale-1 lsb -1 lsb + full scale 111...111 zero - full scale zero 011...111 + 1 / 2 full scale zero - full scale ? invert msb with external inv erter to obtain ctc coding. gaindrift ? fsr ?? c ? fsr ------------------------------- - 10 6 ? = ? offset ?? c ? fsr ------------------------------------- 10 6 ? = ? v ref ?? c ?? ? v ref --------------------------------------- 10 6 ? = ? v o ?? c ?? ? fsr -------------------------------- 10 6 ? = ? fullscalerange 100 ? fsr nominal ?? --------------------------------------------------------------- --- - ? v s 100 ? v s (nominal) --------------------------------- - --------------------------------------------------------------- ---- =
hi-dac80v fn3110 rev 2.00 page 6 of 8 march 2001 times and fast switching will re duce glitches considerably. (measured as one half the product of duration and amplitude.) decoupling and grounding for best accuracy and high frequency performance, the grounding and decoupling scheme shown in figure 1 should be used. decoupling capacitors s hould be connected close to the hi-dac80v (preferably to the device pins) and should be tantalum or electrolytic bypasse d with ceramic types for best high frequency noise rejection. reference supply an internal 6.3v reference is provided on board the hi-dac80v. the voltage (pin 24) is accurate to ? 0.8% and must be connected to the reference input (pin 16) for specified operation. this reference may be used externally, provided current drain is limited to 2.5ma. an external buffer amplifier is recommended if this reference is to be used t o drive other system components. otherwise, var iations in the load driven by the reference will result in gain variations of the hi-dac80 v. all gain adjustments should be made under constant load conditions. output voltage ranges 18 19 20 15 - + -v s +v s 0.01 ? f 1 ? f 14 21 22 0.01 ? f 1 ? f 24 16 figure 1. table 2. range connections range connect pin 15 pin 17 pin 19 unipolar 0 to +5v 18 nc 20 0 to +10v 18 nc nc bipolar ? 2.5v 18 20 20 ? 5v 18 20 nc ? 10v 19 20 15 table 3. gain and offset calibrations unipolar calibration step 1: offset turn all bits off (11 . . . 1) adjust r2 for 0v out step 2: gain turn all bits on (00 . . . 0) adjust r1 for fs - 1 lsb that is: 4.9988 for 0 to +5v range 9.9976 for 0 to +10v range bipolar calibration step 1: offset turn all bits off (11 . . . 1) adjust r2 for negative fs that is: -10v for ? 10v range -5v for ? 5v range -2.5v for ? 2.5v range step 2: gain turn all bits on (00 . . . 0) adjust r1 for positive fs - 1 lsb that is: +9.9951v for ? 10v range +4.9976v for ? 5v range +2.4988v for ? 2.5v range this bipolar procedure adjusts the output range end points. the maximum error at zero (half sca le) will not exceed the linearit y error. see the accuracy specifications. 18 19 20 15 - + 6.3k 21 - + control amp 3.9 m ? r2 +v s -v s 12.6k ? r1 +v s -v s 2.8m ? 0.01 ? f 10k ? to 100k ? 24 17 16 23 5k ? 5k ? 5k ? to 100k ? figure 2. hi-dac80v
hi-dac80v fn3110 rev 2.00 page 7 of 8 march 2001 die characteristics die dimensions 108 mils x 163 mils metallization type: al thickness: 16k ? ? 2k ? tie substrate to ground passivation type: nitride over silox nitride thickness: 3.5k ? ? 0.5k ? silox thickness: 12k ? ? 1.5k ? metallization mask layout hi-dac80v bit 3 bit 2 bit 1 (msb) 6.3v ref out gain adjust +v s common summing junction 20v span 10v span bipolar offset ref in v out -v s bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4
fn3110 rev 2.00 page 8 of 8 march 2001 hi-dac80v intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2001. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between eng lish and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated i n jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrus ions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. damb ar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e24.6 (jedec ms-011-aa issue b) 24 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.150 1.290 29.3 32.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n24 249 rev. 0 12/93
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